library IEEE; 
use IEEE.STD_LOGIC_1164.all; 
use IEEE.STD_LOGIC_ARITH.all; 
use IEEE.STD_LOGIC_UNSIGNED.all; 

entity counter_Testbench is
end counter_Testbench;

architecture counter_with_clock of counter_Testbench is
    
    component clock
        port (clk : out std_logic);
    end component;

    component counter
        Port (clk_in : in STD_LOGIC;
              rst : in STD_LOGIC;
              B   : inout STD_LOGIC_VECTOR (3 downto 0));
    end component;
   component ParallelToSerial 
    Port ( clk           : in  STD_LOGIC;             
           reset         : in  STD_LOGIC;                  
           parallel_in   : inout  STD_LOGIC_VECTOR (7 downto 0); 
           counter_in   : in  STD_LOGIC_VECTOR (3 downto 0);
           serial_out    : out STD_LOGIC:= '0');                  
   end component;

   component SerialToParallel is
    Port ( clk           : in  STD_LOGIC;                  
           reset         : in  STD_LOGIC;                 
           parallel_out  : out  STD_LOGIC_VECTOR (7 downto 0);--:="00000000"; 
           counter_in   : in  STD_LOGIC_VECTOR (3 downto 0); 
           serial_in    : in STD_LOGIC :='0'  );               
          
   end component;
    signal clk2counter : std_logic;
    signal counter_in_out : STD_LOGIC_VECTOR (3 downto 0); 
    signal reset1 : std_logic;
    signal myout : std_logic;
    signal parallel_set : STD_LOGIC_VECTOR (7 downto 0);--:="00000000";
    signal parallel_output : STD_LOGIC_VECTOR (7 downto 0);--:="00000000";
begin
    
    
    clock1: clock port map (clk => clk2counter);
    counter1: counter port map (clk_in => clk2counter, rst=> reset1,B=>counter_in_out);
    PTS : ParallelToSerial port map(clk=>clk2counter,reset =>reset1,parallel_in => parallel_set, counter_in=>counter_in_out,serial_out=>myout);
    STP : SerialToParallel port map(clk=>clk2counter,reset =>reset1,parallel_out => parallel_output,counter_in=>counter_in_out,serial_in=>myout);
    reset1 <= '0';
    --parallel_set<= "10011111";
    --myout<= 	'0';
    --parallel_output <= "00000000";
    		
	process 
	begin
	wait;
	end process;



end architecture counter_with_clock;